The present invention relates to a single-chip microcomputer and, more particularly, to a technique which is effective when applied to a high-performance and high-function single-chip microcomputer suited for a home game machine or a portable data communication terminal device.
There is a single-chip microcomputer or a single-chip data processor in which a central processing unit, a dynamic memory access controller, (as will be shortly referred to as the xe2x80x9cDMACxe2x80x9d) and a peripheral circuit such as a variety of timers are constructed into a semiconductor integrated circuit device.
An example of this single-chip microcomputer is disclosed in xe2x80x9cHITACHI Single-Chip RISC Microcomputer SH7032, SH7034 HARDWARE MANUALxe2x80x9d issued by Hitachi Ltd., in March, 1993.
Thanks to development of the semiconductor technology, a number of semiconductor elements can be formed over one semiconductor substrate. As a result, around the central processing unit, there can be formed its peripheral circuits to enhance the performance and function. If, however, a number of peripheral circuits are simply packaged for the higher performance and more functions, it has been found that disadvantages are caused from the standpoint of the operation speed or the power dissipation. Moreover, this microcomputer has to have its three-dimensional image processing function enhanced.
An object of the present invention is to provide a single-chip microcomputer which can realize a high performance and multiple functions.
Another object of the present invention is to provide a single-chip microcomputer which can realize a high operation speed and a low power dissipation.
Still another object of the present invention is to provide a user-friendly single-chip microcomputer.
A further object of the present invention is to provide a single-chip microcomputer which is enabled by a simple construction to enlarge the operation margin and access a synchronous dynamic type RAM (i.e., Random Access Memory).
A further object of the present invention is to provide a single-chip microcomputer which can execute a three-dimensional image processing at a high speed.
The aforementioned and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
A representative of the invention to be disclosed herein will be briefly described in the following. Specifically, an internal bus is divided into three: the first bus is connected with a central processing unit and a cache memory, and the second bus is connected with a dynamic memory access controller and an external bus interface. The first bus and the second bus are equipped with a break controller having a bus transceiver function to connect the first address bus and the second address bus selectively. The third bus given a lower speed than the first and second bus cycles is connected with peripheral modules. There is provided a bus state controller for data transfers and synchronizations between the second bus and the third bus.
By dividing the internal bus into three buses, according to the above-specified means, the load capacity of a signal transmission path can be reduced to effect the signal transmissions at a high speed. Moreover, the consumption of current through the peripheral modules required to have no high operation speed can be reduced because the peripheral modules are isolated.
Another representative of the invention to be disclosed herein will be briefly described in the following. Specifically, the internal bus is divided into three: the first bus is connected with a central processing unit and a fixed point type multiply and accumulate arithmetic unit, and the second bus is connected with a fixed point type divider unit.
According to the above-specified means, the first bus is connected with the fixed point type multiply and accumulate arithmetic unit so that the multiply and accumulate arithmetic operations can be accomplished at a high speed with a small number of cycles. The second bus is connected with the fixed point type divider unit, in which the arithmetic result is subjected to a dividing operation while another multiply and accumulate operations can be being carried out in parallel, so that a three-dimensional image processing can be accomplished at a high speed.
Still another representative of the invention to be disclosed herein will be briefly described in the following. Specifically, the peripheral modules to be connected with the third bus are exemplified by at least one of a free running timer, a serial communication interface and a watch-dog timer.
According to the above-specified means, the peripheral modules to be connected with the third bus are the free running timer, the serial communication interface and/or the watch-dog timer, which have no direct participation in the speed-up of the data processing, so that they can be given low-speed bus cycles. Thus, the existing peripheral modules can be used as they are without following the high speed of the central processing unit, to make the design efficient and to reduce the power dissipation in the peripheral modules.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, the aforementioned break controller is given a function to monitor the rewrite of the data of the cache memory by the dynamic memory access controller.
According to the above-specified means, the break of the cache data due to the rewrite of the data of the cache memory by the dynamic memory access controller can be detected while speeding up the operation and reducing the power dissipation by dividing the internal bus.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, each of the aforementioned circuit blocks is constructed of a full static type CMOS circuits and is equipped with an operation mode controller including a register for controlling the feed/stop of a clock pulse.
According to the above-specified means, the clock can be fed to only the necessary circuit block so that the power dissipation can be reduced.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, the aforementioned external bus interface is given the burst read mode and the single-write mode of the synchronous dynamic type RAM, and the interface function to access the dynamic type RAM and a pseudo-static type RAM directly.
According to the above-specified means, the synchronous dynamic type RAM, the dynamic RAM and the pseudo-static type RAM can be directly connected by the external bus interface, to improve the user-friendliness.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, the external bus interface produces a clock pulse, which has its phase advanced from the clock pulse of the central processing unit, and feeds it to the clock terminal of the synchronous dynamic type RAM.
According to the above-specified means, the synchronous dynamic type RAM can be accessed by the clock pulse, which has its phase advanced from the clock pulse of the central processing unit, so that its operation margin can be enlarged.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, a matching is given among the data to be read out in the burst read mode of the synchronous dynamic type RAM, the data of one block of the aforementioned cache memory, and the data transfer unit by the dynamic memory access controller.
According to the above-specified means, the data to be read out in the burst read mode of the synchronous dynamic type RAM, the data of one block of the aforementioned cache memory, and the data transfer unit by the dynamic memory access controller are made to have equal data, so that an efficient data transfer can be accomplished.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, the external bus interface is equipped with a memory control signal generator for generating a control signal necessary for setting the operation mode of the synchronous dynamic type RAM by using an address signal partially, when the central processing unit is started by accessing a predetermined access space to set a row address strobe signal (i.e., RAS), a column address strobe signal (i.e., CAS) and a write enable signal (i.e., WE) to the low level.
According to the above-specified means, the synchronous dynamic type RAM can have its modes easily set by the central processing unit.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, the aforementioned cache memory is constructed of a plurality of tag memories and data memories corresponding to the tag memories. These tag memories and data memories are composed of CMOS static type memory cells. A sense amplifier for amplifying the read signals of the memory cells is exemplified by a CMOS sense amplifier having a CMOS latch circuit and a power swatch MOSFETs composed of P-channel type MOS FETs and N-channel type MOSFETs for feeding the operation current to the CMOS latch circuit.
According to the above-specified means, the sense amplifier is constructed of the CMOS latch circuit so that no DC current can flow after a signal amplification to reduce the power dissipation.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, only such one of the plurality of data memories as corresponds to a hit signal coming from the tag memory is activated.
According to the above-specified means, only the data memory corresponding to the hit signal coming from the tag memory can be activated to reduce the power dissipation.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, the plurality of data memories invalidate the transmission of all or a portion of the hit signals from the tag memory by the cache controller to make a direct access possible by the central processing unit.
According to the above-specified means, the plurality of data memories of the cache memory can be wholly or partially used as an internal RAM so that the manners of use can satisfy the various requests of users.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, in a single-chip microcomputer including a central processing unit and a cache memory, the cache memory is exemplified by CMOS static type memory cells as memory elements, and a sense amplifier for amplifying the read signal is exemplified by a CMOS sense amplifier composed of a CMOS latch circuit, P-channel type and N-channel type MOSFETs for feeding the operation current to the CMOS latch circuit.
According to the above-specified means, in the single-chip microcomputer including the central processing unit and the cache memory, the CMOS latch circuit is used in the amplification portion of the sense amplifier of the cache memory so that no DC current can flow after the signal amplification of the sense amplifier to reduce the power dissipation.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, only such one of the plurality of data memories as corresponds to the hit signal corresponding to the hit signal coming from the tag memory is activated.
According to the above-specified means, in the single-chip microcomputer having the cache memory packaged therein, only the data memory corresponding to the hit signal can be activated to reduce the power dissipation.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, a first external terminal and a second external terminal are switched for a bus request signal and a bus acknowledge signal, respectively, when a slave mode is set according to a bus use priority control signal, and the first external terminal and the second external terminal are switched for a bus grant signal and a bus release signal, respectively, when a master mode is set.
According to the above-specified means, one single-chip microcomputer can be used for both the slave mode and the master mode in accordance with the bus use priority control signal, and the terminals are switched for use. As a result, the external terminals can be reduced in number and easily connected to improve the user-friendliness.
A further representative of the invention to be disclosed herein will be briefly described in the following. Specifically, of the three-dimensional image processings, the clipping processing of the data of a coordinate point having been perspectively transformed and the coordinate transformation processing for transforming a coordinate point intrinsic to a predetermined object into a coordinate having a specified view point as an origin point cooperatively with a multiply and accumulate unit are accomplished by the central processing unit in parallel with the perspective transformation processing of the coordinate point having been subjected to the coordinate transformation processing by a divider unit.
According to the above-specified means, while the clipping processing and the coordinate transformation processing of the three-dimensional image processing are being performed by the central processing unit and the multiply and accumulate operation unit, the perspective transformation processing taking a longer time is performed in parallel by the divider unit so that a high-speed three-dimensional image processing can be realized.